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FA3686V
s Description
FA3686V is a PWM type DC-to-DC converter control IC with 2ch outputs that can directly drive power MOSFETs. CMOS devices with high breakdown voltage are used in this IC and low power consumption is achieved. This IC is suitable for very small DC-to-DC converters because of their small and thin package (1.1mm max.), and high frequency operation (to 1.5MHz). This IC contains built-in an error amplifier for series regulators, therefore, this IC is suitable for the 3ch power supply with a 2ch DC-to-DC converter and a 1ch series regulator.
CMOS IC For Switching Power Supply Control FA3686V
s Dimensions, mm TSSOP-16
16 9
* Wide range of supply voltage: VCC=2.5 to 20V * MOSFET direct driving * Low operating current consumption by CMOS process: 3.0mA (typ.) * 2ch PWM control IC * High frequency operation: 300kHz to 1.5MHz * Simple setting of operation frequency by timing resistor * Built-in error amplifier for series regulator * Soft start function on each channel (1ch, 2ch only) * Maximum output duty cycle: 85% (typ.), at 500kHz * Built-in under voltage lockout * High accuracy reference voltage: VREF: 1.00V1%, VREG: 2.20V1% * Timer latch for short-circuit protection with counter * PGS pin for a power supply fault signal * Thin and small package: TSSOP-16
5
0.100.05
1
0.105 to 0.145
s Features
8
4.4 6.40.2
0~8
0.50.08
0.220.02
0.65
s Block diagram
Pin No. Pin symbol Description 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 FB3 IN3FB2 IN2PGS VCC CS2 OUT2 OUT1 CS1 GND RT VREG IN1FB1 TL Ch.3 output of error amplifier Ch.3 inverting input to error amplifier Ch.2 output of error amplifier Ch.2 inverting input to error amplifier PGS signal output Power supply Soft start for Ch.2 Ch.2 output Ch.1 output Soft start for Ch.1 Ground Oscillator timing resistor Regulated voltage output Ch.1 inverting input to error amplifier Ch.1 output of error amplifier Timer latched short circuit protection
1.1max
1
FA3686V
s Absolute maximum ratings
Item
Power supply voltage PGS pin voltage FB1, IN1-, FB2, IN2-, FB3, IN3- pin voltage CS1, CS2, RT, TL, VREG pin voltage OUT1/2 OUT pin source current OUT pin sink current OUT1/2 OUT pin source current OUT pin sink current Power dissipation * Operating junction temperature Operating ambient temperature Storage temperature
* Derating factor Ta 25C: 3mW/C
Symbol VCC VPGS VEA_IN VCTR_IN IOUT- IOUT+ IOUT- IOUT+ Pd TJ TOPR TSTG
Rating 20 20 -0.3 to 5.0 -0.3 to 5.0 -400 (peak) 150 (peak) -50 (continuous) 50 (continuous) 300 (Ta 25C) +125 -30 to +85 -40 to +125
Unit V V V V mA mA mA mA mW C C C
Maximum power dissipation curve
Maximun power dissipation [mW]
350 300 250 200 150 100 50 0 -30 0 30 60 90 120 150
Ambient temperature [C]
s Recommended operating conditions
Item Supply voltage CS1, CS2, TL pin voltage IN1-, IN2-, IN3- pin voltage Oscillation frequency VREG pin capacitance VREG pin current VCC pin capacitance CS1 pin capacitance CS2 pin capacitance Symbol VCC VCTR_IN VEA_IN fOSC CREG IREG CVCC CCS1 CCS2 Between CS1 and GND Between CS2 and VREG 1.0 0.01 0.01 Vcc<10V 10V Vcc<18V Test condition Min. 2.5 0.0 0.0 300 0.1 0.47 500 1.0 1.0 Typ. Max. 18 2.5 2.5 1500 4.7 4.7 1.0 Unit V V V kHz F F mA F F F
s Electrical characteristics (VCC=3.3V, CREG=1.0F, RT=12k, Ta=+25C) Regulated voltage for internal control blocks (VREG pin)
Item Regulated voltage Line regulation Load regulation Variation with temperature Symbol VREG VREG_LINE VREG_LOAD VREG_TC VCC=2.5 to 18V IREG=0 to 1mA Ta=-30 to +85C -5 Test condition Min. 2.178 Typ. 2.200 5 -1 0.5 Max. 2.222 15 Unit V mV mV %
2
FA3686V
Oscillator section (RT pin)
Item Oscillation frequency Line regulation Variation with temperature Symbol fOSC fOSC_LINE fOSC_TC1 VCC=2.5 to 18V Ta=-30 to +85C Test condition Min. 435 Typ. 500 1 3 Max. 565 5 Unit kHz % %
Error amplifier section (IN1-, FB1, IN2-, FB2, IN3-, FB3 pin)
Item Reference voltage (CH.1) Reference voltage (CH.2) Reference voltage (CH.3) VREF VREF Line regulation Variation with temperature Symbol VREF1 VREF2 VREF3 VREF_LINE VREF_TC1 IIN- AVO fT ISIFB ISOFB VFBx=0.5V, VINx-=VREG *4 VFBx=VREG-0.5V, VINx-=0V *4 2.3 -360 Test condition *1 *2 *3 VCC=2.5 to 18V Ta=-30 to +85C VINx-=0.0 to 2.5V *4 Min. 0.99 0.98 0.98 Typ. 1.00 1.00 1.00 2 0.5 0.0 70 1.5 3.5 -270 4.7 -180 Max. 1.01 1.02 1.02 5 Unit V V V mV % mA dB MHz mA A
Input bias current Open loop gain Unity gain bandwidth Output current (sink) Output current (source)
*1 *2 *3 *4
The FB1 voltage is measured under the condition that IN1- pin and FB1 pin are shorted. The input offset voltage of the error amplifier is included. The FB2 voltage is measured under the condition that IN2- pin and FB2 pin are shorted. The input offset voltage of the error amplifier is included. The FB3 voltage is measured under the condition that IN3- pin and FB3 pin are shorted. The input offset voltage of the error amplifier is included. The "x" of INx- and FBx refers to 1 to 3.
Soft start section (CS1, CS2 pin)
Item Threshold voltage (CS1) Symbol VCS1D0 VCS1D20 VCS1D80 Threshold voltage (CS2) VCS2D0 VCS2D20 VCS2D80 Charge current of CS2 (source) Charge current of CS2 (sink) ICS1 ICS2 Test condition Duty cycle=0%, VFB1=1.4V Duty cycle=20%, VFB1=1.4V Duty cycle=80%, VFB1=1.4V Duty cycle=0%, VFB2=0.7V Duty cycle=20%, VFB2=0.7V Duty cycle=80%, VFB2=0.7V VCS1=0.5V VCS2=VREG-0.5V 1.20 0.84 -2. 1.5 0.89 1.25 Min. Typ. 0.82 0.925 1.285 1.33 1.235 0.875 -2.0 2.0 1.27 0.91 -1.5 2.4 0.96 1.32 Max. Unit V V V V V V A A
Pulse width modulation (PWM) section (FB1, FB2 pin)
Item Max. duty cycle of OUT1 Symbol DMAX1 Test condition fOSC=300kHz RT=12k (fOSC 500kHz) fOSC=1.5MHz Max. duty cycle of OUT2 DMAX2 fOSC=300kHz RT=12k (f Threshold voltage of FB1 VFB1D0 VFB1D20 VFB1D80 Threshold voltage of FB2 VFB2D0 VFB2D20 VFB2D80
OSC
Min. 80
Typ. 87 85 78 88
Max. 90
Unit % % % %
500kHz)
80
85 73 0.82 0.925 1.285 1.33 1.235 0.875
90
% % V V V V V V
fOSC=1.5MHz Duty cycle=0% Duty cycle=20% Duty cycle=80% Duty cycle=0% Duty cycle=20% Duty cycle=80%
3
FA3686V
Timer latch protection section (TL pin)
Item Threshold voltage of FB1 Threshold voltage of FB2 Threshold voltage of FB3 Threshold voltage of CS1 Threshold voltage of CS2 TL pin voltage for counting 16th stage TL pin voltage counting 17th stage
*1 *2 *3 *4
Symbol VTHFB1TL VTHFB2TL VTHFB3TL VVTHCS1TL VVTHCS2TL VTL16 VTL17
Test condition *1 *2 *1 *3 *4
Min. 1.5 0.2 1.5 0.2 1.5 0 VREG-0.2
Typ.
Max. 2.0 0.6 2.0 0.6 2.0 0.2 VREG
Unit V V V V V V V
The latched mode operates when the voltage of FB1 or FB3 exceeds the threshold voltage as shown in the table. The latched mode operates when the FB2 voltage falls below the threshold voltage as shown in the table. The timer latch of FB1 is disabled when the CS1 voltage is below the threshold voltage as shown in the table. The timer latch of FB2 is disabled when the CS2 voltage is above the threshold voltage as shown in the table.
Under voltage lockout circuit section (VCC pin)
Item ON threshold voltage of VCC Hysteresis voltage Symbol VUVLO VUVLO Test condition Min. 2.0 Typ. 2.2 0.1 Max. 2.35 Unit V V
PGS section (VCC, PGS pin)
Item Threshold voltage of VCC Hysteresis voltage VPGS variation with temperature On resistance Symbol VPGS VPGS VPGS_TC1 RPGS Test condition VCC decreasing VCC increasing Ta=-30 to +85C VCC=2.2V, IPGS=10mA Min. 2.15 Typ. 2.25 0.10 1 50 100 Max. 2.35 Unit V V %
Output section (OUT1, OUT2 pin)
Item High side on resistance of OUT1/2 Symbol RONHI Test condition IOUTx=-50mA * IOUTx=-50mA, VCC=5V * IOUTx=-50mA, VCC=15V * Low side on resistance of OUT1/2 RONLO IOUTx=50mA * IOUTx=50mA, VCC=5V * IOUTx=50mA, VCC=15V * Rise time of OUT1/2 Fall time of OUT1/2
* The "x" of OUTx refers to 1, 2.
Min.
Typ. 10 9 8 5 5 5 25 40
Max. 20
Unit
10
ns ns
tRISE tFALL
CL=1000pF CL=1000pF
Overall section
Item Supply current Symbol ICCA ICCA1 ICCA2 ICCA3 Test condition Ch.1, Ch.2 operating mode Ch.1, Ch.2 off mode Ch.1, Ch.2 operating mode, VCC=18V Latch mode Min. Typ. 3.0 2.5 3.5 2.5 Max. 4.0 Unit mA mA mA mA
4
FA3686V
s Characteristic curves Oscillation frequency vs. timing resistor VCC=3.3V, Ta=25C
1800
Oscillation frequency vs. supply voltage VCC Ta=25C, RT=12k (fOSC=500kHz)
510
Oscillation frequency [kHz]
Oscillation frequency [kHz]
1600 1400 1200 1000 800 600 400 200 0 1 10 100
508 506 504 502 500 498 496 494 492 490 0 5 10 15 20
Vcc [V]
Timing resistor RT [k]
Oscillation frequency vs. ambient temperature VCC=3.3V, RT=12k (fOSC=500kHz)
570
Regulated voltage vs. supply voltage VCC Ta=25C, RT=12k (fOSC=500kHz)
2.23
Oscillation frequency [kHz]
Regulated voltage VREG [V]
550 530 510 490 470 450 430 -50 -25 0 25 50 75 100 125 150
2.22 2.21 2.20 2.19 2.18 2.17 0 5 10
Load current IREG=0A
Ambient temperature Ta [C]
15
20
Vcc [V]
Regulated voltage vs. ambient temperature VCC=3.3V, RT=12k (fOSC=500kHz)
2.23
Regulated voltage vs. load current VCC=3.3V, RT=12k (fOSC=500kHz)
2.23
Regulated voltage VREG [V]
2.22 2.21 2.20 2.19 2.18 2.17 -50 -25 0 25 50 75 100 125 150
Regulated voltage VREG [V]
2.22
Ta=85C
2.21 2.20
Ta=25C
2.19
Ta=-30C
2.18 2.17 0.0 0.2 0.4 0.6 0.8 1.0 1.2
Ambient temperature Ta [C]
Load current IREG [mA]
5
FA3686V
Reference voltage vs. supply voltage VCC Ta=25C, RT=12k (fOSC=500kHz)
1.020
Reference voltage vs. ambient temperature VCC=3.3V, RT=12k (fOSC=500kHz)
1.020
Reference voltage VREF [V]
1.010 1.005 1.000 0.995 0.990 0.985 0.980 0 5 10 15 20 25
Reference voltage VREF [V]
1.015
1.015 1.010 1.005 1.000 0.995 0.990 0.985 0.980 -50 -25 0 25 50 75 100 125 150
Vcc [V]
Ambient temperature Ta [C]
Error amp. output current (sink) vs. ambient temperature VCC=3.3V, RT=12k (fOSC=500kHz)
5.0 4.5 4.0 3.5 3.0 2.5 2.0 -50 -25 0 25 50 75 100 125 150
Error amp. output current (source) vs. ambient temperarure VCC=3.3V, RT=12k (fOSC=500kHz)
-150
Output current (source) ISOFB [uA]
Output current (sink) ISIFB [mA]
-200
-250
-300
-350 -50
-25
0
25
50
75
100
125
150
Ambient temperature Ta [C]
Ambient temperature Ta [C]
Charge current of CS1 (source) vs. ambient temperature VCC=3.3V, RT=12k (fOSC=500kHz)
Charge current of CS1 (source) ICS1 [uA]
-1.0
Charge current of CS2 (sink) vs. ambient temperature VCC=3.3V, RT=12k (fOSC=500kHz)
Charge current of CS2 (sink) ICS2 [uA]
3.0
-1.5
2.5
-2.0
2.0
-2.5
1.5
-3.0 -50
-25
0
25
50
75
100
125
150
1.0 -50
-25
0
25
50
75
100
125
150
Ambient temperature Ta [C]
Ambient temperature Ta [C]
6
FA3686V
Output duty cycle vs. CS voltage (ch. 1) VCC=3.3V, Ta=25C
100 90
Output duty cycle vs. oscillation frequency (ch. 1) VCC=3.3V, Ta=25C
100
fosc=300kHz
fosc=500kHz fosc=760kHz
Output duty cycle (ch.1) [%]
90 80 70 60 50 40 30 20 10 0
VCS1=1.30V VCS1=1.25V VCS1=1.20V VCS1=1.15V VCS1=1.10V VCS1=1.05V VCS1=1.00V VCS1=0.95V VCS1=0.90V VCS1=0.85V
Output duty cycle (ch.1) [%]
80 70 60 50 40 30 20 10 0 0.80 0.90 1.00 1.10 1.20 1.30 1.40 1.50
fosc=1.5MHz
300
500
700
900
1100
1300
1500
VCS1 [V]
Oscillation frequency [kHz]
Output duty cycle vs. CS voltage (ch. 2) VCC=3.3V, Ta=25C
100 90
Output duty cycle vs. oscillation frequency (ch. 2) VCC=3.3V, Ta=25C
100 90 80 70 VCS2=0.85V VCS2=0.90V VCS2=0.95V VCS2=1.00V VCS2=1.05V 50 VCS2=1.10V 40 30 20 10 VCS2=1.15V VCS2=1.20V VCS2=1.25V VCS2=1.30V
fosc=300kHz fosc=500kHz
Output duty cycle (ch.2) [%]
80 70 60 50 40 30 20 10 0 0.70
fosc=1.5MHz
0.80
0.90
1.00
1.10
1.20
1.30
1.40 0 300 500 700 900 1100 1300 1500
VCS2 [V]
Duty 2 [%]
fosc=760kHz
60
Oscillation frequency [kHz]
Maximum duty cycle vs. oscillation frequency (ch. 1) VCC=3.3V, Ta=25C
95 90 85
Maximum duty cycle vs. oscillation frequency (ch. 2) VCC=3.3V, Ta=25C
95 90 85
DMAX1 [%]
DMAX2 [%]
80 75 70 65 300 500 700 900 1100 1300 1500
80 75 70 65 300
500
700
900
1100
1300
1500
Oscillation frequency [kHz]
Oscillation frequency [kHz]
7
FA3686V
Maximum duty cycle vs. ambient temperature (ch. 1) VCC=3.3V, RT=12k (fOSC=500kHz)
90 89 88 87
Maximum duty cycle vs. ambient temperature (ch. 2) VCC=3.3V, RT=12k (fOSC=500kHz)
90 89 88 87
DMAX1 [%]
86 85 84 83 82 81 80 -50 -25 0 25 50 75 100 125 150
DMAX2 [%]
86 85 84 83 82 81 80 -50 -25 0 25 50 75 100 125 150
Ambient temperature Ta [C]
Ambient temperature Ta[C]
OUT1 terminal source current vs. H level output voltage Ta=25C
0 -50 -100 -150
OUT2 terminal source current vs. H level output voltage Ta=25C
0
-50
Vcc=2.5V
-100 -150
Vcc=2.5V
IOUT1 [mA]
-200 -250 -300 -350 -400 -450 -500 0.0 1.0 2.0
IOUT2 [mA]
Vcc= 3V
-200 -250 -300 -350
Vcc= 3V
Vcc= 5V Vcc=12V
Vcc= 5V Vcc=12V
-400 -450 -500
3.0
4.0
5.0
6.0
0.0
1.0
2.0
3.0
4.0
5.0
Vcc-VOUT1 [V]
Vcc-VOUT2 [V]
OUT1 terminal source current vs. H level output voltage VCC=3.3V
0
OUT2 terminal source current vs. H level output voltage VCC=3.3V
0
-50
-50
IOUT1 [mA]
Ta=85C
-150
IOUT2 [mA]
-100
-100
Ta=85C
-150
-200
Ta=-30C
Ta=25C
-200
Ta=25C Ta=-30C
-250
-250
-300 0.0 0.5 1.0 1.5 2.0 2.5 3.0
-300 0.0 0.5 1.0 1.5 2.0 2.5 3.0
Vcc-VOUT1 [V]
Vcc-VOUT2 [V]
8
FA3686V
OUT1 terminal source current vs. H level output voltage VCC=12V
0
OUT2 terminal source current vs. H level output voltage VCC=12V
0
-100
-100
IOUT1 [mA]
-200
IOUT2 [mA]
-200
-300
Ta=85C Ta=-30C Ta=25C
-300
Ta=85C Ta=-30C
-400
-400
Ta=25C
-500 0.0 1.0 2.0 3.0 4.0 5.0
-500 0.0 1.0 2.0 3.0 4.0 5.0
Vcc-VOUT1 [V]
Vcc-VOUT2 [V]
OUT1 terminal sink current vs. L level voltage
OUT2 terminal sink current vs. L level voltage
200
200
Ta=-30C Ta=25C
150
150
Ta=-30C
Ta=25C
IOUT1 [mA]
IOUT2 [mA]
Ta=85C
100
Ta=85C
100
50
50
0 0.0
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
VOUT1 [V]
VOUT2 [V]
OUT1 terminal rise time vs. supply voltage VCC CL=1000pF
60
OUT2 terminal rise time vs. supply voltage VCC CL=1000pF
60
OUT1 terminal rise time t RISE [ns]
50
OUT2 terminal rise time t RISE [ns]
50
Ta=85C
40
Ta=25C
40 30 20
Ta=85C Ta=25C
30
Ta=-30C
20
Ta=-30C
10
10 0
0 0 5 10 15 20
0
5
10
15
20
Vcc [V]
Vcc [V]
9
FA3686V
OUT1 terminal fall time vs. supply voltage VCC CL=1000pF
200
OUT2 terminal fall time vs. supply voltage VCC CL=1000pF
200
OUT1 terminal fall time t FALL [ns]
Ta=85C
150
OUT2 terminal fall time t FALL [ns]
Ta=85C
150
Ta=25C
100
Ta=25C
100
Ta=-30C
Ta=-30C
50
50
0 0 5 10 15 20
0 0 5 10 15 20
Vcc [V]
Vcc [V]
Operating mode supply current vs. oscillation frequency Ta=25C
Operating mode supply current ICCA [mA]
6.0
Operating mode supply current vs. ambient temperature
Vcc=18V Vcc=12V
5.0
Operating mode supply current ICCA [mA]
4.5
4.0
Vcc=12V
Vcc=5V
4.0
3.5
Vcc=3.3V
Vcc=5V
3.0
3.0
Vcc=2.5V
Vcc=3.3V
2.5
Vcc=2.5V
2.0 300
2.0 -50
-25
0
25
50
75
100
125
150
500
700
900
1100
1300
1500
Oscillation frequency [kHz]
Ambient temperature Ta [C]
UVLO ON threshold vs. ambient temperature
PGS terminal on resistance vs. ambient temperature
2.5
80 70 60
UVLO ON threshold VUVLO [V]
2.4 2.3 2.2 2.1 2.0 1.9 1.8 -50
Vcc= 5V
Vcc=3.3V
RPGS []
50
Vcc=2.5V
40 30 20 10 0 -50
-25
0
25
50
75
100
125
150
-25
0
25
50
75
100
125
150
Ambient temperature Ta [C]
Ambient temperature Ta [C]
10
FA3686V
PGS terminal current vs. voltage Ta=25C
45
PGS terminal threshold voltage of VCC vs. ambient temperature
2.35
Vcc=7.0V
40 35 30
Vcc=5V Vcc=3.3V VPGS [V]
2.30
IPGS [mA]
25 20 15 10 5
2.25
Vcc=2.2V
2.20
vcc=1.8V vcc=1.5V
2.15 -50 -25 0 25 50 75 100 125 150
0 0.0
0.5
1.0
1.5
2.0
2.5
Ambient temperature Ta [C]
VPGS [V]
CS1 internal discharge switch current vs. voltage VCC=3.3V, RT=12k (fOSC=500kHz)
400
CS2 internal discharge switch current vs. voltage VCC=3.3V, RT=12k (fOSC=500kHz)
0
Ta=-30C
350 300
-50
Ta=25C Ta=85C
ICS1 off [uA]
250 200 150 100 50 0 0.00
ICS2 off [uA]
-100
Ta=85C
-150
Ta=-30C
0.50 1.00 1.50 2.00 2.50
-200 0.00
Ta=25C
0.50
1.00
1.50
2.00
VCS1 [V]
VREG-VCS2 [V]
Error amplifier gain and phase vs. frequency
11
FA3686V
s Description of each circuit
1. Reference voltage circuit (VREF) This circuit generates the reference voltage of 1.00V (ch1: 1%; ch2, 3: 2%) compensated in temperature from VCC voltage, and is connected to the non-inverting input of the error amplifier. This voltage cannot be observed directly because an external pin for this purpose is not provided. 2. Regulated voltage circuit (VREG) This circuit generates 2.20V1% based on the reference voltage VREF, and is used as the power supply of the internal IC circuits. This voltage is generated when the supply voltage, VCC, is input. The VREG voltage also is used as a regulated power supply for soft start and others. The output current for external circuit should be within 1mA. A capacitor connected between VREG pin and GND pin is necessary to stable the VREF voltage (To determine capacitance, refer to recommended operating conditions). The VREG voltage is regulated in VCC voltage of 2.4V or above. 3. Oscillator The oscillator generates a triangular waveform by charging and discharging the built-in capacitor. A desired oscillation frequency can be set by the value of the resistor connected to the RT pin (Fig. 1). The built-in capacitor voltage oscillates between approximately 0.82V and 1.38V at fosc=500kHz (that of ch1 and ch2 are slightly different) with almost the same charging and discharging gradients (Fig. 2). You can set the desired oscillation frequency by changing the gradients using the resistor connected to the RT pin. (Large RT: low frequency, small RT: high frequency) The oscillator waveform cannot be observed from the outside because a pin for this purpose is not provided. The RT pin voltage is approximately 1V DC in normal operation. The oscillator output is connected to the PWM comparator. 4. Error amplifier circuit The error amplifiers 1, 2, 3 have inverting input pins of IN1- pin (Pin 14), IN2- pin (Pin 4) and IN3- pin (Pin 2). The non-inverting input is internally connected to the reference voltage VREF of the error amplifier 1 (1.00V1%; 25C) and the error amplifiers 2, 3 (1.00V2%; 25C). The FB pins (Pin1, Pin15) are the output of the error amplifiers. An external RC network is connected between FB pin and IN- pin for gain and phase compensation setting. The error amplifier 3 can be used for a series regulator.
OSC
12
RT RT
Fig. 1
RT value: small 1.38V
RT value: large
0.82V
Fig. 2
Vout1
RNF1
R1 Er.Amp.1
14
FB1
15
R2
IN1+
VREG
13
VREF (1.0V)
Comp
R3
IN2Vout3
4
Er.Amp.2 FB2
3
R4 Vout2 R5 R6 RNF3 IN32 1
Er.Amp.3 FB3
RNF2
Fig. 3
12
FA3686V
5. PWM comparator The PWM output generates from the oscillator output, the error amplifier output (FB1, FB2) and CS voltage (CS1, CS2) (Fig. 4). The oscillator output is compared with the preferred lower voltage between FB1 and CS1 for ch1. While the preferred voltage is lower than oscillator output, the PWM output is low. While the preferred voltage is higher than oscillator output, the PWM output is high. Since the phase of Ch2 is the opposite phase of Ch1, higher voltage between FB2 and CS2 is preferred and while the preferred voltage is lower than the oscillator output, the PWM output 2 is high. (Cannot be observed externally) The output polarity of OUT1, OUT2 changes according to the condition of SEL pin. (See Fig. 6) The maximum duty cycle (DMAX1, DMAX2) is internally set approximately 85%. Note that the maximum duty cycle depends on operation frequencies. (See the characteristics curve: Output duty cycle vs. oscillation frequency) 6. Soft start function This IC has a soft start function to protect DC-to-DC converter circuits from damage when starting operation. CS1 pin (Pin10) and CS2 pin (Pin7) are used for soft start function of ch1 and ch2 respectively. (Fig. 5) When the supply voltage is applied to the VCC pin and UVLO is cancelled, the capacitor CCS1 and CCS2 is charged by the internal constant current sources (2A, typ.). Then, the CS1 voltage gradually increases, and the CS2 voltage gradually decreases. Since the CS1, and CS2 are connected to the PWM comparator, the pulses gradually widen and then the soft start function operates. (Fig. 6)
PWM output1 Nch. drive CS1 Oscillator output DMAX1 UVLO DMAX2 CS2 PWM output2 Pch. drive PWM Comp.2 OUT2
8
FB1
PWM Comp.1
OUT1
9
FB2
Fig. 4
VREG
13
13
VREG CCS2
10
7
CS1 CCS1
CS2
Fig. 5
Er. amp.1 output Oscillator output CS1 pin voltage
PWM output 1
OUT1 Nch.drive
CS2 pin voltage Oscillator output Er. amp.2 output
PWM output2
OUT2 Pch. drive
Fig. 6
13
FA3686V
7. Timer latch short-circuit protection circuit This IC has the timer latch short-circuit protection circuit. The circuit cuts off the output of all channels when the output voltage of DC-to-DC converter drops due to short circuit or overload. Delay time of the timer latch mode is set by a counter system in the internal circuit, therefore, no external parts are necessary. When one of the output voltage of the DC-to-DC converter drops due to a short circuit or overload, the FB1 and FB3 pin voltage increases up to around the VREG voltage for ch1 and ch3, or the FB2 pin voltage drops down to around 0V for ch2. The counter system operates when the FB1 or FB3 pin voltage exceeds the timer latch threshold voltage of 2.0V(max.) or FB2 pin voltage falls below timer latch threshold voltage of 0.2V(min.). The counter system counts oscillator waveform. If this system counts the oscillation cycles of 216 times (TL pin: GND, 16th stage counter) or 217 times (TL pin: VREG, 17th stage counter), this circuit detects short circuit. Then the IC is set to off latch mode and the output of all channels is shut off and the current consumption becomes 2.5mA (typ.). (Fig. 7) If the DC-to-DC converters return to normal before counter system counts 216 or 217, counter is reset. The period (tp) between the occurrences of short-circuit in the converter output and setting to off latch mode can be calculated by the following equations: tp [s] = 216 1 fosc 1 fosc
TL pin: GND
FB2 Short circuit Time t
Ch1
Momentary short circuit
Short circuit
FB1 or 3 Oscillator output
Timer latch count
tp Timer latch count Short circuit protection Time t Off latch mode
OUT1
Time t
Ch2
Timer latch count Timer latch count tp Short circuit protection
Oscillation output
tp [s] = 217
TL pin: VREG
Momentary short circuit OUT2
Example. When fosc=500kHz and TL pin to GND, the period tp is: tp=216 1/500kHz=0.131sec. You can reset off latched mode of the short-circuit protection by either of the following ways to 1) CS pins, or 2) VCC pin: 1) Set the CS pin of the cause of off latch mode as follows. CS1 pin voltage = 0V, CS2 pin voltage = VREG 2) VCC voltage is below UVLO off threshold voltage (2.1V typ.). Connect the TL pin to either VREG or GND. If TL pin is opened, the counter operation is unstable. 8. Output circuit The IC contains a push-pull output stage and can directly drive MOSFETs. The maximum peak current of the output stage is sink current of +150mA, and source current of -400mA. The IC can also drive NPN and PNP transistors. The maximum current in such cases is 50mA. You must design the output current considering the rating of power dissipation. (See "Design advice".) 9. Undervoltage lockout circuit The IC contains an undervoltage lockout circuit to protect the circuit from the damage caused by malfunctions when the supply voltage drops. When the supply voltage rises from 0V, the IC starts to operate at VCC of 2.2V (typ.) and outputs generate pulses. If a drop of the supply voltage occurs, it stops output at VCC of 2.1V (typ.). When it occurs, the CS1 pin is turned to low level and the CS2 pin to high level, and then these pins are reset.
Off latch mode
Time t
Fig. 7
14
FA3686V
10. PGS circuit The PGS pin is an open drain output of Nch MOSFET for transmitting fault signals of the power supply. The PGS circuit is enabled when Vcc voltage is over the operating threshold voltage (approximately 1V). The Nch MOSFET turns ON and the PGS pin is connected to GND if any of the following three conditions occurs: 1) the VCC voltage is below the threshold voltage (VCC increasing: 2.35V typ.; VCC decreasing: 2.25V typ.), 2) UVLO turns on (VCC=2.1V or below), 3) IC is off latch mode. The operation sequence is shown in Fig. 8. As shown in Fig. 8, in the case of increasing the Vcc voltage with the voltage V applied to the PGS pin, when the Vcc voltage reaches 1V, PGS circuit is enabled and detects that the Vcc voltage is not enough high. Then PGS circuit turns the Nch MOSFET on and output fault signal. The fault signal is cancelled when the VCC voltage exceeds 2.35V (typ.). In the case that the VCC voltage exceeds 2.53V (typ.) and the IC is off latch mode, the PSG circuit detects it as abnormal and the Nch MOSFET is turned on. In the case of decreasing the VCC voltage, the circuit sends out fault signals when the VCC voltage is below 2.25V (typ.) and continues to output until the VCC voltage reaches below the PGS circuit operation threshold voltage of approximately 1V. (Under the VCC voltage of 1V, the circuit does not operate normally.)
PGS
5 UVLO VPGS Timer latch 11
+
V
Vcc voltage stable state
Hysteresis voltage
Vcc VPGS voltage 2.25V
VCC increasing
Off latch mode reset
VCC decreasing
Off latch mode 1V
PGS pin voltage
V
PGS operation
PGS operation
PGS operation
Fig. 8
15
FA3686V
s Design advice
1. Setting the oscillation frequency As described in item 1, "Description of each circuit," a desired oscillation frequency can be determined by the value of the resistor connected to the RT pin. When designing an oscillation frequency, you can set any frequency between 300kHz and 1.5MHz. You can obtain the oscillation frequency from the characteristic curve "Oscillation frequency (fosc) vs. timing resistor resistance (RT)" or the value can be approximately calculated by the following expression. fOSC = 4050 RT = RT -0.86
1.16
VCC pin voltage Threshold voltage CS1 pin voltage
VCS1n
()
4050 fOSC
fOSC: Oscillation frequency [kHz] RT: Timing resistor [k]
t0
t
Fig. 9
This expression, however, can be used for rough calculation, the obtain value is not guaranteed. The operation frequency varies due to the conditions such as tolerance of the characteristics of the ICs, influence of noises, or external discrete components. When determining the values, examine the effectiveness of the values in an actual circuit. The timing resistor RT should be wired to the GND pin as shortly as possible because the RT pin is a high impedance pin and is easy affected by noises. 2. Determining soft start period The period from the start of charging the capacitor CCS to widening n% of output duty cycle can be roughly calculated by the following expression: (see Fig. 5 for symbols) t [s] = VCS2n CCS1 ICS1 (VREG - VCS2n) ICS2
For CS1 pin
t [s] =
CCS1
For CS2 pin
CCS1, CCS2: Capacitance connected to the CS1 or CS2 pin [F] ICS1, ICS2: CS charge current [A] (2A typ.)
VCS1n and VCS2n are the voltage of the CS1 and CS2 pins in n% of output duty cycle, and vary in accordance with operating frequency. The value can be obtained from the characteristic curve "Output duty cycle vs. CS voltage" The charging of the CCS1 and CCS2 starts after the UVLO is unlocked. Therefore, the period from power-on of VCC to widening n% of output duty cycle is the sum of t0 and t. To reset the soft start function, the supply voltage VCC is lowered below the UVLO voltage (2.1V typ.) and then the internal switch discharges the CS capacitor. The characteristics of the internal switch for discharge are shown in following the characteristics curves of "Characteristics of CS1 internal discharge switch current vs. voltage" and "Characteristics of CS2 internal discharge switch current vs. voltage". Therefore, when determining the period of soft start at restarting the power supply, consider the characteristics carefully.
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FA3686V
3. Determining the output voltage of DC-DC converters The ways to determine the output voltage of the DC-DC converter of each channel is shown in Fig. 10 and the following equations. For ch1: The output voltage of a boost circuit is determined by: Vout1 = R1 + R2 R2 VREF
VREG
13 8
Vout1
9
OUT1 Vout1
R1 IN114 15
FB1
+
R2 VREF (1.0V)
OUT2 Vout2
For ch2: The output voltage of an inverting circuit is determined by: Vout2 = R3 + R4 R3 VREF - R4 R3 VREG
R3 IN24 3
FB2
+
R4 VREF (1.0V) Vout2
Vout3
The ratio of resistances is determined by: R3 VREG - VREF = R3 Vout2 + VREF
(Use the absolute value of the Vout2 voltage.)
Vout3
R5 IN32 1
FB3
+
R6 VREF (1.0V)
For ch3: The output voltage of a series regulator is determined by: Vout3 = R5 + R6 R6
Fig. 10
VREF
4. Restriction of external discrete components and recommended operating conditions To achieve a stable operation of the IC, the value of external discrete components connected to VCC, VREG, CS pins should be within the recommended operating conditions. And the voltage and current applied to each pin should be also within the recommended operating conditions. If the pin voltage of OUT1, OUT2, or VREG becomes higher than the VCC pin voltage, the current flows from the pins to the VCC pin because parasitic three diode exist between the VCC pin and these pins. Be careful not to allow this current to flow. 5. Loss calculation of IC Since it is difficult to measure IC loss directly, the calculation to obtain the approximate loss of the IC connected directly to a MOSFET is described below. When the supply voltage is VCC, the current consumption of the IC is ICCA, the total input gate charge of the driven MOSFET is Qg and the switching frequency is fsw, the total loss Pd of the IC can be calculated by: Pd VCC (ICCA + Qg fsw). The value in this expression is influenced by the effects of the dependency of supply voltage, the characteristics of temperature, or the tolerance of parameter. Therefore, evaluate the appropriateness of IC loss sufficiently considering the range of values of above parameters under all conditions. Example: ICCA=3.0mA for VCC=3.3V in the case of a typical IC from the characteristics curve. Qg=6nC, fsw=500kHz, the IC loss "Pd" is as follows. Pd 3.3 (3.0mA + 6nC 500kHz) 19.8mW If two MOSFETs are driven under the same condition for 2 channels, Pd is as follows: Pd 3.3 {3.0mA + 2 (6nC 500kHz)} = 29.7mW
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FA3686V
s Application circuit
10V/5mA
0.1uF 0.1uF 4700pF 10k 13k 4.7uF 180k
0.1uF
0.1uF
2.9 to 3.6V
4k 1000pF 15uF 10uF 470 1k
5.0V/200mA
GND
-5.0V/100mA
1000pF 470 2.2k 11k
FB1 IN1- VREG RT GND CS1 OUT1
FB3 IN3- FB2 IN2- PGS VCC CS2 OUT2
10uF
8
10
FA3686V
11
6
7
0.022uF
9
0.047uF
12
12k
0.47uF
PGS
33k 10k
13
1uF 10k
14
3
4
5
2200pF
2
15
4700pF
1
4700pF
16
47k
TL
4.7k
Parts tolerances characteristics are not defined in the circuit design sample shown above. When designing an actual circuit for a product, you must determine parts tolerances and characteristics for safe and economical operation.
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